HMC703LP4E【PDF 25/58 页】IC FRACT-N PLL W/SWEEPR 24QFN

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Sheet目录1996

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6 - 31

HMC703LP4E

v02.0813

8 GHz fractional syntHesizer

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 978-250-3373 fax Order On-line at www.hittite.com

Application Support: pll@hittite.com

ref Path ’r’ Divider

The reference path “R” divider is based on a 14 bit counter and can divide input signals of up to 350 MHz input by values

from 1 to 16,383 and is controlled by Reg 02h[13:0]. The reference divider output may be viewed in test mode on the

LD_sDO pin, by setting Reg 0Fh[4:0] = 9d.

The HMC703LP4E can use the undivided reference, while exporting a divided version for auxiliary purposes (eg. ramp

triggers, FPGAs etc.) on the GPO, if Reg 06h[21] = 1.

rf Path

The RF path is shown in Figure 36. This path features a low noise 8 GHz RF input buffer followed by an 8 GHz RF

divide-by-2 with a selectable bypass. If the VCO input is below 4 GHz the RF divide-by-2 should be by-passed for

improved performance in fractional mode. The RF divide-by-2 is followed by the N divider, a 16 bit divider that can

operate in either integer or fractional mode with up to 4 GHz inputs. Finally the N divider is followed by the Phase

Detector (PD), which has two inputs, the RF path from the VCO (V) and the reference path (R) from the crystal. The PD

can operate at speeds up to 100 MHz in fractional Mode B (recommended ), 80 MHz in fractional Mode A and 115 MHz

in integer mode.

Figure 36. RF Path

rf input stage

The RF input stage provides the path from the external VCO to the phase detector via the RF or ’N’ divider. The RF

input path is rated to operate up to 8 GHz across all conditions. The RF input stage is a differential common emitter

stage with internal DC bias, and is protected by EsD diodes as shown in Figure 37. This input is not matched to 50 . A

100 resistor placed across the inputs can be used for a better match to 50 . In most applications the input is used

single-ended into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking

capacitor. The preferred input level for best spectral performance is -10 dBm nominally.

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